There has been known an error detection and correction technique using error check and correction (ECC) as measures against errors in data stored in a dual inline memory module (DIMM). An example of such an error detection and correction technique is the single error correction/double error detection (SEC-DED) coding technique in which 8-bit ECC is added to 64-bit data to correct 1-bit error and detect two-bit error.
Moreover, there has been known a technique of increasing the number of bits of detectable errors without reducing the encoding ratio by concurrently operating a plurality of DIMMs using the memory lock step technology and by storing data and ECC in the DIMMs operated concurrently. For example, two DIMMs of a 72-bit width are concurrently operated and 128-bit data and 16-bit ECC are stored separately in the two DIMMs so that an S8EC (144, 128) code for detecting continuous 8-bit error is constructed. Related techniques are disclosed in Japanese National Publication of International Patent Application No. 2010-537311 and Japanese Laid-open Patent Publication No. 2012-177964.